1. Field of the Invention
The present invention generally relates to Built-In Self-Test (BIST), and particularly relates to scheduling test execution during a BIST routine.
2. Relevant Background
Built-In Self-Test (BIST) is a methodology that enables a device such as an integrated circuit, board or system to test itself. Built-in test equipment, hereinafter referred to as a BIST engine, includes hardware and/or software incorporated into a device for providing BIST capability. BIST may be used to test memory, digital logic, analog, or mixed-signal portions of an integrated circuit. Conventional BIST engines comprise a test pattern generator, an output-response analyzer and a BIST state machine. Under control of the BIST state machine, the output-response analyzer observes the response of a device to a sequence of tests generated by the test pattern generator. If the device's response matches an expected response, then it passes the BIST routine. Otherwise, the device fails.
Low-complexity BIST engines execute a sequence of available hard-coded and/or quasi-programmable tests at speeds supported by the corresponding circuit under test. Some tests may be hard-coded in the sense that their content becomes unalterable once the BIST engine design is finalized. Other tests may be quasi-programmable in that their content may be partially (but not fully) programmable after design finalization, e.g., their data pattern may be altered but not how the data is loaded and corresponding results stored. Conventionally, slower external test equipment is used only to initiate a BIST routine, e.g., by providing seed values to the BIST engine. Once initialized, the BIST engine executes the available tests at high speeds, thus reducing test time. However, the order in which tests are executed by low-complexity BIST engines is conventionally fixed, and thus cannot be altered once the design of the BIST engine is finalized.
However, the ideal content and order of a BIST routine may not be determinable until after the design has been completed and actual hardware produced. For example, circuit simulation during the design phase cannot with complete accuracy predict all possible functional conditions of the circuit being designed. In addition, process variations may cause unforeseen or unpredictable behavior. As such, a more complete understanding of a circuit's functional behavior is not known until after the circuit has been built and fully characterized. This includes determining an ideal test execution order for a BIST routine.
For example, it may be later determined that a particular test execution order set during the design process may not be ideal in that the tests most likely to detect a fail are not scheduled early in a conventional fixed-order BIST routine. As such, numerous BIST test cycles pass before executing the tests most likely to detect a fail, thus reducing the efficiency of conventional low-complexity BIST engines. Further, it may be discovered post-design completion that certain tests included in a fixed-order BIST routine may not detect fails, rarely detect fails or are redundant. However, such tests are conventionally executed by low-complexity BIST engines despite their later discovered inefficiency.
Complex BIST engines provide greater test flexibility by implementing a single test program that is fully programmable. Unlike low-complexity BIST engines, their more complex counterparts do not execute a sequence of tests. Instead, equipment external to the BIST engine programs the content associated with a single test program to be executed. As such, the test program may be altered or reprogrammed without requiring re-design of the BIST engine. However, many tester cycles are consumed programming the contents of a complicated BIST test program via external equipment. Further, external test equipment used to load BIST program content conventionally functions at speeds much slower than that of the internal circuitry associated with the circuit under test. As a result, the test time needed to ‘upload’ the content of a programmable BIST routine from a tester to a circuit under test can be lengthy, thus increasing overall cost of a circuit under test. In addition, a single programmable BIST test must be programmed multiple times to ensure proper test coverage.